INTRODUCING | The 18SCT005A, a high-voltage monitor capable of 1200V at 0.7% accuracy.
INTRODUCING
The 18SCT005A, a high-voltage monitor capable of 1200V at 0.7% accuracy
INTRODUCING
The 18SCT005A, a high-voltage monitor capable of 1200V at 0.7% accuracy
Elizabeth Brown, Power Systems Design, July 2026
As EV battery voltages continue climbing to 800V, 1,000V, and beyond, the sensing function tasked with monitoring that voltage must scale alongside it, without inheriting the drift, bulk, and complexity of discrete resistors. The 18SCT005 demonstrates that high-voltage sensing can be condensed into a single, low-cost IC without compromising accuracy, temperature stability, or transient response. As OEMs and Tier 1 suppliers design the next generation of battery management systems, inverters, and onboard chargers, a monolithic approach like this offers a simple path to a smaller, more reliable, and easier-to-validate high-voltage measurement chain, exactly the kind of building block to support the next wave of EV platforms.
Samir Jaber, Wevolver.com, May 2026
High-voltage systems are central to modern engineering across electric mobility, industrial power electronics, and medical equipment. These systems rely on accurate voltage measurement to operate within safe limits, maintain efficiency, and respond to changing conditions. High-voltage values feed directly into control loops, protection logic, and diagnostic routines. Any deviation between actual and measured voltage introduces uncertainty that propagates through the system.
Scaling high-voltage down to a measurable range appears straightforward at first glance. In practice, this task involves maintaining an accurate ratio with voltage, preserving stability across temperature, and ensuring that measurement remains reliable over time. These requirements place high-voltage sensing in a different category than for low-voltage measurement. The constraints are tighter, the consequences of error are more serious, and the design trade-offs are more complex.
Samir Jaber, Wevolver.com, May 2026
Innovations in semiconductors are being shaped by first-principles engineering, systems thinking, and leadership models built for long-term resilience. This edition explores how physics-driven manufacturing, values-based operations, human-centered engineering, and systems-first chip design are helping deep-tech organizations simplify complexity and build smarter, more reliable technologies for the future.
Samir Jaber, Wevolver.com, March 2026
How SimpleChips designs high-voltage silicon for systems that must perform reliably over decades
Samir Jaber, Wevolver.com, January 2026
Alain R. Comeau, and Jacques Laneuville, IEEE Transactions on Semiconductor Manufacturing, Vol. 5, No. 3, August 1992.
A test chip (named Yieldchip) was designed, simulated, fabricated, and tested on a 3- mu m process. The layout of the Yieldchip’s cells enables the test program to electrically locate and identify active faults, thereby automating the, classification of defects. The Yieldchip can detect more than one defect per circuit in most circumstances. The algorithm can identify the 21 simple defects of the cells and can be used as an expert system to extend this list. Unidentified detectable faults are flagged at all times and located if possible.
Alain R. Comeau, Journal of Electrochemical Society, Vol. 139, No. 5, May 1992
The addition of a ramped nucleation cycle, just after an initial oxidation, is shown to greatly increase the precipitation of interstitial oxygen during simulated processing on N/N+ antimony doped epitaxial wafers. When used with fully processed wafers, the ramped nucleation improves internal gettering. Oxygen precipitate density and bulk stacking fault density achieved are about a factor of 100 higher when using ramped nucleation. These results indicate that N/N+ antimony doped epitaxial wafers have an intrinsic gettering capability as good as that of lightly doped material when using an activation cycle (initial oxidation) and subsequent ramped nucleation. A method for calculating bulk stacking fault density is presented. It is shown that, at high concentration (above 107 cm−3), the square of the bulk stacking fault length is inversely proportional to their density. This finding indicates that the growth of bulk stacking faults is limited by the supply of interstitial silicon generated in the bulk during oxygen precipitate growth.
Alain R. Comeau and Normand Nadeau, IEEE Transactions on Semiconductor Manufacturing, Vol. 4, No. 2, May 1991.
Alain R. Comeau, IEEE Transactions on Semiconductor Manufacturing, Vol. 3, No. 2, May 1990.
